1. FIELD OF THE INVENTION
This invention relates to testing of complex integrated circuits, and more particularly to integrated test structures in a microprocessor.
2. DESCRIPTION OF THE RELATED ART
Integrated circuits (IC's) such as microprocessors are increasing in complexity at a dizzying pace. A central processing unit (CPU) or microprocessor can easily have over a million transistors, all of which must function properly. Ideally, each transistor and each wiring connection should be tested at the factory before the microprocessor chip is sold to a computer manufacturer.
Since the microprocessor chip may have only a few hundred input/output (I/O) pins, most of the transistors to be tested are deeply embedded in the chip. Often complex sequences of test vectors or stimuli must be input to the chip to test embedded circuitry. These complex test sequences increase the amount of time a chip spends on a test machine and thus increases test cost, which is a significant fraction of the total cost of a chip.
Circuitry is often added to complex IC's to improve testability. This test circuitry provides a more direct path to deeply embedded circuits so that test stimuli can be more directly applied to the embedded circuitry. Test circuitry also routes the outputs of deeply embedded circuits to the I/O pins. Special automatic-test-program-generator (ATPG) software is used to create the test stimuli.
SCAN CHAINS
A common prior-art approach is to add a scan chain to a complex IC. Most of the flip-flops on the chip are modified to have additional test inputs and an additional test output. Each test input is directly connected to the test output of another flip-flop so that the flip-flops in the chip form a chain. See the examples in "Dual Latch Clocked LSSD and Method" by Yurash, U.S. Pat. No. 5,463,338 assigned to VLSI Technology, Inc. of San Jose, Calif.
A test-mode or scan clock is routed to each modified flip-flop. When the scan clock is pulsed, the data from one flip-flop is shifted to the next flip-flop in the chain, from the test output of one flip-flop to the test input of the next flip-flop. Data from any flip-flop in the scan chain can eventually be shifted to the end of the chain, which is connected to an I/O pad. Thus any flip-flop can be observed for test by pulsing the shift clock enough times. The microprocessor can be clocked using the normal CPU clock any number of times to bring the chip in to a desired state, and then the CPU clock is stopped and the scan clock is pulsed to shift out the scan chain.
Data can also be shifted into any flip-flop in the scan chain when another I/O pad is connected to the test input of the first flip-flop in the chain. Thus each modified flip-flop can be controlled and observed using scan chain techniques.
FIG. 1 illustrates a scan chain in a complex microprocessor chip. CPU core 14 is embedded in a larger chip, and is clocked during normal operation by a CPU clock CPUCLK. Many flip-flops in CPU core 14 are modified to have an additional test or scan input SI and a scan output SO. A test or scan clock SCLK is routed to each modified flip-flop 12. When CPUCLK is stopped and SCLK is pulsed, the SI input is loaded into flip-flop 12. Each modified flip-flop 12 has its scan output SO connected to the scan input SI of the next modified flip-flop 12. I/O pad 16 drives the SI input of the first flip-flop 12 in the chain, while the last flip-flop 12 has its SO coupled to drive I/O pad 18.
SCAN FLIP-FLOP--FIG. 2
FIG. 2 is a diagram of a flip-flop modified for testing in a scan chain. Flip-flop 12 has a master latch 20 and a slave latch 22. Together, master latch 20 and slave latch 22 form a standard edge-triggered flip-flop. Standard output Q from slave latch 22 changes on the rising edge of CPUCLK, while the output of master latch 20 changes when CPUCLK is low.
Multiplexer or mux 26 is added in front of the D input to master latch 20. Mux 26 connects the standard D input to master latch 20 during normal operation, but the scan-in input SI is connected to master latch 20 during test mode. A scan-enable signal TSEL controls mux 26 to select the test input during scan-test mode. When CPUCLK is paused in the low state, the scan input SI is loaded into master latch 20 during test mode to control the state of slave latch 22 on the next rising edge of CPUCLK.
Data is shifted through the scan chain when scan clock SCLK is pulsed, loading scan latch 24 with SI. NOR gate 19 inverts and passes SCLK or CPUCLK through to master latch 20. CPUCLK may be alternately pulsed with SCLK, or other clocking schemes may be used. Many variations are possible, such as using a single clock without a separate scan clock, or replacing scan latch 24 with a gate.
SCAN LATCH INCREASES AREA, COST, DELAYS
While inserting modified scan flip-flops into embedded circuitry greatly increases testability, the additional mux and scan latch can increase the chip die area and thus the cost. The performance of the microprocessor during normal operation can also be harmed due to the additional loading of the slave latch, and the longer wiring traces on the larger die.
SCAN CHAINS LONGER AS COMPLEXITY INCREASES
As the complexity of the IC increases, more flip-flops are used. Thus the length of the scan chain grows as more flip-flops need to be included in the chain. It is not unusual for a CPU core to have 10,000 flip flops. When all flip-flops are connected together in a long chain, a huge number of scan-clock cycles are needed to shift data in and out of the chain. When 10,000 clock cycles are required to load or read the state of the CPU core through the long scan chain, test time rapidly increases as more circuitry is tested. Clearing or presetting the flip-flops could require many cycles.
The scan chain can be split into several smaller links, but additional circuitry or I/O pins are needed. The large number of flip-flops also increases the loading and delay for SCLK. Another problem realized by the inventors is the power surge when SCLK is pulsed. Pulsing 10,000 flip-flops at the same time creates a di/dt problem resulting in severe ground bounce and possible loss of stored data.
NON-FLIP-FLOP TEST POINTS NOT TESTED
While the scan chain can load and observe flip-flops, testing and debugging is more efficient if other nodes on the circuit are directly observable. For example, the data value on an internal bus is useful to a debugger, but if the bus is not clocked into a flip-flop, the scan chain does not observe it. Thus internal signal nodes rather than just flip-flops are desirable as test points.
The scan chain is useful for fully synchronous designs using a strict clocking scheme, but circuit designers often break the rules. Speed-critical parts of the design may not use strict clocking and flip-flops, but instead use latches (half of a flip-flop). Cycle-stealing is common in very high speed design, where a latch rather than a full flip-flop is used to "steal" available path delay from a following stage. These and other design tricks do not fit easily into scan-chain testing.
What is desired is a test structure to observe and load latches as well as flip-flops. It is desired to eliminate the scan latch added to a flip-flop for scan-chain testing. It is desirable to observe non-storage nodes such as busses and signals using the same kind of test structure for testing flip-flops. It is desired that the test structure be a regular structure to minimize wiring lengths and propagation delays. It is desirable to eliminate long scan chains, but instead have smaller groups of test points which can be selected for testing. It is desired to reduce the current spike when the test clock is pulsed.